COP888EB datasheet(26/75 Pages) NSC

26 / 75 page

Functional Block Description of

the CAN Interface (Continued)

HALT mode (the CAN receive wakeup will still work) in order

to reduce current consumption and to assure a proper resy-

chronization to the bus after exiting the HALT mode.

Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE

(independent of the values of the TxEN1 and TxEN0 bits).

RXREF1 Reference voltage applied to Rx1 if bit is set

RXREF0 Reference voltage applied to Rx0 if bit is set

FMOD

Fault Confinement Mode select

Setting the FMOD bit to “0” (default after power on reset) will

select the Standard Fault Confinement mode. In this mode

the device goes from “bus off” to “error active” after monitor-

ing 128*11 recessive bits (including bus idle) on the bus. This

mode has been implemented for compatibility with existing

solutions. Setting the FMOD bit to “1” will select the En-

hanced Fault Confinement mode. In this mode the device

goes from “bus off” to “error active” after monitoring 128

“good” messages, as indicated by the reception of 11 con-

secutive “recessive” bits including the End of Frame,

whereas the standard mode may time out after 128 x 11 re-

cessive bits (e.g., bus idle).

TRANSMIT CONTROL/STATUS (TCNTL) (00AB)

NS1

NS0

TERR

RERR

CEIE

TIE

RIE

TXSS

Bit 7

Bit 0

NS1..NS0

Node Status, i.e., Error Status.

TABLE 7. Node Status

NS1

NS0

Output

Error active

Error passive

Bus off

The Node Status bits are read only.

TERR

Transmit Error

This bit is automatically set when an error occurs during the

transmission of a frame. TERR can be programmed to gen-

erate an interrupt by setting the Can Error Interrupt Enable

bit (CEIE). This bit must be cleared by the user’s software.

Note: This is used for messages for more than two bytes. If an error occurs

during the transmission of a frame with more than 2 data bytes, the us-

er’s software has to handle the correct reloading of the data bytes to

the TxD registers for retransmission of the frame. For frames with 2 or

fewer data bytes the interface logic of this chip does an automatic re-

transmission. Regardless of the number of data bytes, the user’s soft-

ware must reset this bit if CEIE is enabled. Otherwise a new interrupt

will be generated immediately after return from the interrupt service

routine.

RERR

Receiver Error

This bit is automatically set when an error occurred during

the reception of a frame. RERR can be programmed to gen-

erate an interrupt by setting the Can Error Interrupt Enable

bit (CEIE). This bit has to be cleared by the user’s software.

CEIE

CAN Error Interrupt Enable

If set by the user’s software, this bit enables the transmit and

receive error interrupts. The interrupt pending flags are

TERR and RERR. Resetting this bit with a pending error in-

terrupt will inhibit the interrupt, but will not clear the cause of

the interrupt (RERR or TERR). If the bit is then set without

clearing the cause of the interrupt, the interrupt will reoccur.

TIE

Transmit Interrupt Enable

If set by the user’s software, this bit enables the transmit in-

terrupt. (See TBE and TXPND.) Resetting this bit with a

pending transmit interrupt will inhibit the interrupt, but will not

clear the cause of the interrupt. If the bit is then set without

clearing the cause of the interrupt, the interrupt will reoccur.

RIE

Receive Interrupt Enable

If set by the user’s software, this bit enables the receive in-

terrupt or a remote transmission request interrupt (see RBF,

RFV and RRTR). Resetting this bit with a pending receive in-

terrupt will inhibit the interrupt, but will not clear the cause of

the interrupt. If the bit is then set without clearing the cause

of the interrupt, the interrupt will reoccur.

TXSS

Transmission Start/Stop

This bit is set by the user’s software to initiate the transmis-

sion of a frame. Once this bit is set, a transmission is pend-

ing, as indicated by the TXPND flag being set. It can be reset

by software to cancel a pending transmission. Resetting the

TXSS bit will only cancel a transmission, if the transmission

of a frame hasn’t been started yet (bus idle), if arbitration has

been lost (receiving) or if an error occurs during transmis-

sion. If the device has already started transmission (won ar-

bitration) the TXPND and TXSS flags will stay set until the

transmission is completed, even if the user’s software has

written zero to the TXSS bit. If one or more data bytes are to

be transmitted, care must be taken by the user, that the

Transmit Data Register(s) have been loaded before the

TXSS bit is set. TXSS will be cleared on three conditions

only: Successful completion of a transmitted message; suc-

cessful cancellation of a pending transmision; Transition of

the CAN interface to the bus-off state.

Writing a zero to the TXSS bit will request cancellation of a

pending transmission but TXSS will not be cleared until

completion of the operation. If an error occurs during trans-

mission of a frame, the logic will check for cancellation re-

quests prior to restarting transmission. If zero has been writ-

ten to TXSS, retransmission will be canceled.

RECEIVE/TRANSMIT STATUS (RTSTAT) (Address

X’00AC)

TBE

TXPND

RRTR

ROLD

RORN

RFV

RCV

RBF

Bit 7

Bit 0

This register is read only.

TBE

Transmit Buffer Empty

This bit is set as soon as the TxD2 register is copied into the

Rx/Tx shift register, i.e., the 1st data byte of each pair has

been transmitted. The TBE bit is automatically reset if the

TxD2 register is written (the user should write a dummy byte

to the TxD2 register when transmitting an odd number of

bytes of zero bytes). TBE can be programmed to generate

DS012837-52

FIGURE 17. Acceptance Filter Block-Diagram

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