COP888EB datasheet(12/75 Pages) NSC

12 / 75 page

Pin Description (Continued)

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

SI (MICROWIRE Serial Data Input)

SK (MICROWIRE Serial Clock)

SO (MICROWIRE Serial Data Output)

T1A (Timer I/O)

(Timer T1 Capture Input)

Dedicated WATCHDOG output

INTR (External Interrupt Input)

Port G has the following dedicated function:

CKO Oscillator dedicated output

Port M is a bidirectional I/O, it may be configured in software

as Hi-Z input, weak pull-up, or push-pull output. These pins

may be used as general purpose input/output pins or for se-

lected altlernate functions.

Port M pins have optional alternate functions. Each pin

(M0–M5) has been assigned an alternate data, configura-

tion, or wakeup source. If the respective alternate function is

selected the content of the associated bits in the configura-

tion and/or data register are ignored. If an alternate wakeup

source is selected the input level at the respective pin will be

ignored for the purpose of triggering a wakeup event, how-

ever it will still be possible to read that pin by accessing the

input register. The SPI (Serial Peripheral Interface) block, for

example, uses four of the Port M pins to automatically re-

configure its MISO (Master Input, Slave Output), MOSI

(Master Output, Slave Input), SCK (Serial Clock) and Slave-

Select pins as inputs or outputs, depending on whether the

interface has been configured as a Master or Slave. When

the SPI interface is disabled those pins are available as gen-

eral purpose I/O pins configurable by user software writing to

the associated data and configuration bits. The CAN inter-

face on the device makes use of one of the Port M’s alter-

nate wake-ups, to trigger a wakeup if such a condition has

been detected on the CAN’s dedicated receive pins.

Port M has the following alternate pin functions:

Multi-input Wakeup or CAN

Multi-input Wakeup

Multi-input Wakeup or T2B

Multi-input Wakeup or T2A

Multi-input Wakeup or SS

Multi-input Wakeup or SCK

Multi-input Wakeup or MOSI

Multi-input Wakeup or MISO

Ports C, E, F and N are general-purpose, bidirectional I/O

ports.

Any device package that has Port C, E, F, M, N but has fewer

than eight pins, contains unbonded, floating pads internally

on the chip. For these types of devices, the software should

writea1tothe configuration register bits corresponding to

the non-existent port pins. This configures the port bits as

outputs, thereby reducing leakage current of the device.

Port N is an 8-bit wide port with alternate function capability

used for extending the slave select (SS) lines of the on SPI

interface. The SPI expander block provides mutually exclu-

sive slave select extension signals (ESS0 to ESS7) accord-

ing to the state of the SS line and specific contents of the SPI

shift register. These slave select extension lines can be

routed to the Port N I/O pins by enabling the alternate func-

tion of the port in the PORTNX register. If enabled, the inter-

nal signal on the ESSx line causes the ports state to change

exactly like a change to the PORTND register. It is the user’s

responsibility to switch the port to an output when enabling

the alternate function.

Port N has the following alternate pin functions:

ESS7

ESS6

ESS5

ESS4

ESS3

ESS2

ESS1

ESS0

CAN pins: For the on-chip CAN interface this device has five

dedicated pins with the following features:

REF

On-chip reference voltage with the value of V

CC/2

Rx0

CAN receive data input pin.

Rx1

CAN receive data input pin.

Tx0

CAN transmit data output pin. This pin may be put in

the TRI-STATE mode with the TXEN0 bit in the CAN

Bus control register.

Tx1

CAN transmit data output pin. This pin may be put in

the TRI-STATE mode with the TXEN1 bit in the CAN

Bus control register.

ALTERNATE PORT FUNCTIONS

Many general-purpose pins have alternate functions. The

software can program each pin to be used either for a

general-purpose or for a specific function. The chip hardware

determines which of the pins have alternate functions, and

what those functions are. This section lists the alternate

functions available on each of the pins.

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more port D outputs (ex-

cept D2) together in order to get a higher drive.

Note: Care must be exercised with D2 pin operation. At RESET, the external

loads on this pin must ensure that the output voltages stay above 0.8

VCC to prevent the chip from entering special modes. Also keep the ex-

ternal loading on D2 to < 1000 pF.

Port I is an 8-bit Hi-Z input port, and also provides the analog

inputs to the A/D converter. If unterminated, Port I pins will

draw power only when addressed.

Functional Description

The architecture of the device utilizes a modified Harvard ar-

chitecture. With the Harvard architecture, the control store

program memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

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