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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COP888EB датащи(PDF) 17 Page - National Semiconductor (TI) |
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COP888EB датащи(HTML) 17 Page - National Semiconductor (TI) |
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17 / 75 page  Timers (Continued) sequently, the TxC0 control bit should be reset when enter- ing the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both whether a TxA input capture or a timer underflow (or both) caused the interrupt. Figure 11 shows a block diagram of the timer in Input Cap- ture mode. TIMER CONTROL FLAGS The control bits and their functions are summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled TxPNDB Timer Interrupt Pending Flag TxENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled DS012837-12 FIGURE 11. Timer in Input Capture Mode www.national.com 17 |
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