COP888EB datasheet(16/75 Pages) NSC

16 / 75 page

Timers (Continued)

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention.

The user only has to define the parameters of the PWM sig-

nal (ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the timer Tx counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Figure 9 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB con-

trol flag is set. The occurrence of the positive edge on the

TxB input pin is latched to the TxPNDB flag.

Figure 10 shows a block diagram of the timer in External

Event Counter mode.

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the in-

put capture mode.

In this mode, the timer Tx is constantly running at the fixed t

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag

TxENA allows the interrupt on TxA to be either enabled or

disabled. Setting the TxENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

TxA pin. Similarly, the flag TxENB controls the interrupts

from the TxB pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

DS012837-10

FIGURE 9. Timer in PWM Mode

DS012837-11

Note: The PWM output is not available in this mode since the TxA pin is

being used as the counter input clock.

FIGURE 10. Timer in External Event Counter Mode

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