PIC17C752-08SLASHCL datasheet(186/328 Pages) MICROCHIP

186 / 328 page

PIC17C7XX

DS30289A-page 186

16.4.1

A/D RESULT REGISTERS

The ADRESH:ADRESL register pair is the location

where the 10-bit A/D result is loaded at the completion

of the A/D conversion. This register pair is 16-bits wide.

The A/D module gives the ﬂexibility to left or right justify

the 10-bit result in the 16-bit result register. The A/D

Format Select bit (ADFM) controls this justiﬁcation.

Figure 16-8 shows the operation of the A/D result justi-

ﬁcation. The extra bits are loaded with ’0’s’. When an

A/D result will not overwrite these locations (A/D dis-

able), these registers may be used as two general pur-

pose 8-bit registers.

16.5

A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switching noise from the conversion. When the conver-

sion is completed the GO/DONE bit will be cleared, and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock source is another clock option (not

RC), a SLEEP instruction will cause the present conver-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

16.6

Effects of a Reset

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is aborted.

The value that is in the ADRESH:ADRESL registers is

not

modiﬁed

for

Power-on

Reset.

The

ADRESH:ADRESL registers will contain unknown data

after a Power-on Reset.

Note:

For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To allow the con-

version to occur during SLEEP, ensure the

SLEEP

instruction immediately follows the

instruction that sets the GO/DONE bit.

FIGURE 16-8: A/D RESULT JUSTIFICATION

10-Bit Result

ADRESH

ADRESL

0000 00

ADFM = 0

2 1 0 7

10-bits

RESULT

ADRESH

ADRESL

10-bits

0000 00

0 7 6 5

RESULT

ADFM = 1

Right Justiﬁed

Left Justiﬁed

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