PIC17C752-08SLASHCL datasheet(150/328 Pages) MICROCHIP

150 / 328 page

PIC17C7XX

DS30289A-page 150

15.2.6

MULTI-MASTER MODE

In multi-master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a reset or

when the MSSP module is disabled. Control of the I2C

bus may be taken when bit P (SSPSTAT<4>) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be moni-

tored, for abitration, to see if the signal level is the

expected output level. This check is performed in hard-

ware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

15.2.7

I2C MASTER MODE SUPPORT

Master Mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting

the SSPEN bit. Once master mode is enabled, the

user has six options.

- Assert a start condition on SDA and SCL.

- Assert a Repeated Start condition on SDA and

SCL.

- Write to the SSPBUF register initiating trans-

mission of data/address.

- Generate a stop condition on SDA and SCL.

- Conﬁgure the I2C port to receive data.

- Generate an Acknowledge condition at the end

of a received byte of data.

Note:

The MSSP Module when conﬁgured in I2C

Master Mode does not allow queueing of

events. For instance: The user is not

allowed to initiate a start condition, and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case the

SSPBUF will not be written to, and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

15.2.7.1

I2C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

Start condition. Since the Repeated Start condition is

also the beginning of the next serial transfer, the I2C

bus will not be released.

In Master Transmitter mode serial data is output

through SDA, while SCL outputs the serial clock. The

ﬁrst byte transmitted contains the slave address of the

receiving device, (7 bits) and the Read/Write (R/W) bit.

In this case the R/W bit will be logic '0'. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master receive mode the ﬁrst byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case the R/W bit will be

logic '1'. Thus the ﬁrst byte transmitted is a 7-bit slave

address followed by a '1' to indicate receive bit. Serial

data is received via SDA while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

The baud rate generator used for SPI mode operation

is now used to set the SCL clock frequency for either

100 kHz, 400 kHz, or 1 MHz I2C operation. The baud

rate generator reload value is contained in the lower 7

bits of the SSPADD register. The baud rate generator

will automatically begin counting on a write to the

SSPBUF. Once the given operation is complete (i.e.

transmission of the last data bit is followed by ACK) the

internal clock will automatically stop counting and the

SCL pin will remain in its last state

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