PIC17C752-08SLASHCL datasheet(116/328 Pages) MICROCHIP

116 / 328 page

PIC17C7XX

DS30289A-page 116

The USART can be conﬁgured as a full duplex asyn-

chronous system that can communicate with peripheral

devices such as CRT terminals and personal comput-

ers, or it can be conﬁgured as a half duplex synchro-

nous system that can communicate with peripheral

devices such as A/D or D/A integrated circuits, Serial

EEPROMs etc. The USART can be conﬁgured in the

following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

The SPEN (RCSTA<7>) bit has to be set in order to

conﬁgure the I/O pins as the Serial Communication

Interface (USART).

The USART module will control the direction of the

RX/DT and TX/CK pins, depending on the states of the

USART conﬁguration bits in the RCSTA and TXSTA

registers. The bits that control I/O direction are:

• SPEN

• TXEN

• SREN

• CREN

• CSRC

FIGURE 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)

RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)

R/W - 0

U - 0

R - 0

R - x

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

R = Readable bit

W = Writable bit

-n = Value at POR reset

(x = unknown)

bit7

bit 0

bit 7:

SPEN: Serial Port Enable bit

1 = Conﬁgures TX/CK and RX/DT pins as serial port pins

0 = Serial port disabled

bit 6:

RX9: 9-bit Receive Select bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5:

SREN: Single Receive Enable bit

This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.

Synchronous mode:

1 = Enable reception

0 = Disable reception

Note: This bit is ignored in synchronous slave reception.

Asynchronous mode:

Don’t care

bit 4:

CREN: Continuous Receive Enable bit

This bit enables the continuous reception of serial data.

Asynchronous mode:

1 = Enable continuous reception

0 = Disables continuous reception

Synchronous mode:

1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)

0 = Disables continuous reception

bit 3:

Unimplemented: Read as '0'

bit 2:

FERR: Framing Error bit

1 = Framing error (Updated by reading RCREG)

0 = No framing error

bit 1:

OERR: Overrun Error bit

1 = Overrun (Cleared by clearing CREN)

0 = No overrun error

bit 0:

RX9D: 9th bit of receive data (can be the software calculated parity bit)

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