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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16C925-S/CL датащи(PDF) 175 Page - Microchip Technology |
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PIC16C925-S/CL датащи(HTML) 175 Page - Microchip Technology |
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175 / 182 page  2001 Microchip Technology Inc. Preliminary DS39544A-page 173 PIC16C925/926 T1CON (Timer1 Control) ............................................ 47 T2CON (Timer2 Control) ............................................ 52 RESET ....................................................................... 97, 101 Block Diagram .......................................................... 101 RESET Conditions for PCON Register .................... 103 RESET Conditions for Program Counter ................. 103 RESET Conditions for STATUS Register ................ 103 Resistor Ladder (LCD) ....................................................... 95 RP1:RP0 (Bank Select) bits ......................................... 12, 19 S SCL ........................................................................ 70, 71, 72 SDA .............................................................................. 71, 72 Slave Mode SCL pin ...................................................................... 70 SDA pin ...................................................................... 70 SLEEP ....................................................................... 97, 101 Software Simulator (MPLAB SIM) .................................... 134 Special Features of the CPU ............................................. 97 Special Function Registers, Summary ............................... 15 SPI Associated Registers ................................................. 64 Master Mode .............................................................. 62 Serial Clock ................................................................ 61 Serial Data In ............................................................. 61 Serial Data Out .......................................................... 61 Serial Peripheral Interface (SPI) ................................ 59 Slave Select ............................................................... 61 SPI Clock ................................................................... 62 SPI Mode ................................................................... 61 SSP Block Diagrams I2C Mode ............................................................ 69 SPI Mode ........................................................... 61 Register Initialization States ............................. 104, 105 SSPADD Register ................................................ 69, 70 SSPBUF Register .................................... 62, 69, 70, 71 SSPCON Register ............................................... 60, 69 SSPIF bit ........................................................ 70, 71, 72 SSPOV bit .................................................................. 70 SSPSR ....................................................................... 62 SSPSR Register .................................................. 70, 71 SSPSTAT ................................................................... 71 SSPSTAT Register ........................................ 59, 69, 71 SSP I2C Addressing ................................................................. 70 Associated Registers ................................................. 72 Multi-Master Mode ..................................................... 72 Reception ................................................................... 71 SSP I2C Operation ..................................................... 69 START ....................................................................... 71 START (S) ................................................................. 72 STOP (P) ................................................................... 72 Transmission .............................................................. 71 SSPEN (Sync Serial Port Enable) bit ................................. 60 SSPM3:SSPM0 .................................................................. 60 SSPOV (Receive Overflow Indicator) bit ........................... 60 SSPOV bit .......................................................................... 70 Stack .................................................................................. 25 Overflows ................................................................... 25 Underflow ................................................................... 25 STATUS Register .............................................................. 19 Initialization States ................................................... 104 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 .......................................................... 60 T TAD .................................................................................... 79 Timer0 Associated Registers ................................................. 45 Block Diagram ........................................................... 41 Clock Source Edge Select (T0SE Bit) ....................... 20 Clock Source Select (T0CS Bit) ................................ 20 External Clock ........................................................... 43 Synchronization ................................................. 43 Timing ................................................................ 43 Increment Delay ........................................................ 43 Initialization States ................................................... 104 Interrupt ..................................................................... 41 Interrupt Timing ......................................................... 42 Prescaler ................................................................... 44 Block Diagram ................................................... 44 Timing ........................................................................ 42 TMR0 Interrupt ........................................................ 108 Timer1 Associated Registers ................................................. 50 Asynchronous Counter Mode .................................... 49 Block Diagram ........................................................... 48 Capacitor Selection ................................................... 50 External Clock Input Synchronized Counter Mode ............................. 48 Timing with Unsynchronized Clock .................... 49 Unsynchronized Clock Timing ........................... 49 Oscillator .................................................................... 50 Prescaler ................................................................... 50 Reading a Free-running Timer .................................. 49 Register Initialization States .................................... 104 Resetting Register Pair .............................................. 50 Resetting with a CCP Trigger Output ........................ 50 Switching Prescaler Assignment ............................... 45 Synchronized Counter Mode ..................................... 48 T1CON Register ........................................................ 47 Timer Mode ............................................................... 48 Timer2 Block Diagram ........................................................... 51 Output ........................................................................ 51 Register Initialization States .................................... 104 T2CON Register ........................................................ 52 Timing Diagrams (Operational) Clock/Instruction Cycle ................................................ 9 I2C Clock Synchronization ......................................... 68 I2C Data Transfer Wait State ..................................... 66 I2C Multi-Master Arbitration ....................................... 68 I2C Reception (7-bit address) .................................... 71 I2C Slave-Receiver Acknowledge .............................. 66 I2C STARTand STOP Conditions .............................. 65 I2C Transmission (7-bit address) ............................... 71 INT Pin Interrupt Timing .......................................... 108 LCD Half-Duty Cycle Drive ........................................ 86 LCD Interrupt Timing in Quarter-Duty Cycle Drive .... 91 LCD One-Third Duty Cycle Drive .............................. 87 LCD Quarter-Duty Cycle Drive .................................. 88 LCD SLEEP Entry/Exit (SLPEN=1) ........................... 93 LCD Static Drive ........................................................ 85 SPI (Master Mode) .................................................... 63 SPI (Slave Mode, CKE = 0) ....................................... 63 SPI (Slave Mode, CKE = 1) ....................................... 64 Successive I/O Operation .......................................... 39 Time-out Sequences on Power-up .......................... 106 Timer0 Interrupt Timing ............................................. 42 Timer0 with External Clock ........................................ 43 |
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