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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16C925-S/CL датащи(PDF) 17 Page - Microchip Technology |
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PIC16C925-S/CL датащи(HTML) 17 Page - Microchip Technology |
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17 / 182 page  2001 Microchip Technology Inc. Preliminary DS39544A-page 15 PIC16C925/926 2.3 Special Function Registers The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for control- ling the desired operation of the device. These regis- ters are implemented as static RAM. The special function registers can be classified into two sets, core and peripheral. Those registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Details on page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 26 01h TMR0 Timer0 Module Register xxxx xxxx 41 02h PCL Program Counter (PC) Least Significant Byte 0000 0000 25 03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 19 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 26 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 29 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31 07h PORTC — — PORTC Data Latch when written: PORTC pins when read --xx xxxx 33 08h PORTD PORTD Data Latch when written: PORTD pins when read 0000 0000 34 09h PORTE PORTE pins when read 0000 0000 36 0Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 25 0Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 21 0Ch PIR1 LCDIF ADIF — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 23 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47 11h TMR2 Timer2 Module Register 0000 0000 51 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 64, 72 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 60 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 58 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 58 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 53 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH A/D Result Register High xxxx xxxx 80, 81 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 0000 75 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These pixels do not display, but can be used as general purpose RAM. |
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