PIC16C925-SSLASHCL datasheet(85/182 Pages) MICROCHIP

85 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 83

PIC16C925/926

11.0

LCD MODULE

The LCD module generates the timing control to drive

a static or multiplexed LCD panel, with support for up to

32 segments multiplexed with up to four commons. It

also provides control of the LCD pixel data.

The interface to the module consists of 3 control regis-

ters (LCDCON, LCDSE, and LCDPS), used to define

the timing requirements of the LCD panel and up to 16

LCD data registers (LCD00-LCD15) that represent the

array of the pixel data. In normal operation, the control

registers are configured to match the LCD panel being

used. Primarily, the initialization information consists of

selecting the number of commons required by the LCD

panel, and then specifying the LCD frame clock rate to

be used by the panel.

Once the module is initialized for the LCD panel, the

individual bits of the LCD data registers are cleared/set

to represent a clear/dark pixel, respectively.

Once

the

module

configured,

the

LCDEN

(LCDCON<7>) bit is used to enable or disable the LCD

module. The LCD panel can also operate during

SLEEP by clearing the SLPEN (LCDCON<6>) bit.

Figure 11-2 through Figure 11-5 provides waveforms

for static, half-duty cycle, one-third-duty cycle, and

quarter-duty cycle drives.

LCDCON REGISTER (ADDRESS 10Fh)

R/W-0

LCDEN

SLPEN

WERR

BIAS

CS1

CS0

LMUX1

LMUX0

bit 7

bit 0

bit 7

LCDEN: Module Drive Enable bit

= LCD drive enabled

= LCD drive disabled

bit 6

SLPEN: LCD Display Enabled to SLEEP bit

= LCD module will stop driving in SLEEP

= LCD module will continue driving in SLEEP

bit 5

WERR: Write Failed Error bit

= System tried to write LCDD register during disallowed time. (Must be reset in software.)

= No error

bit 4

BIAS: Bias Generator Enable bit

= Internal bias generator powered down, bias is expected to be provided externally

= Internal bias generator enabled, powered up

bit 3-2

CS<1:0>: Clock Source bits

= FOSC/256

= T1CKI (Timer1)

= Internal RC oscillator

bit 1-0

LMUX<1:0>: Common Selection bits

Specifies the number of commons

= Static(COM0)

= 1/2

(COM0, 1)

= 1/3

(COM0, 1, 2)

= 1/4

(COM0, 1, 2, 3)

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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