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PIC16C925-S/CL датащи(PDF) 14 Page - Microchip Technology |
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PIC16C925-S/CL датащи(HTML) 14 Page - Microchip Technology |
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14 / 182 page ![]() PIC16C925/926 DS39544A-page 12 Preliminary 2001 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into four banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Func- tion Registers are General Purpose Registers imple- mented as static RAM. All four banks contain special function registers. Some “high use” special function registers are mirrored in other banks for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indi- rectly through the File Select Register FSR (Section 2.6). The following General Purpose Registers are not phys- ically implemented: • F0h-FFh of Bank 1 • 170h-17Fh of Bank 2 • 1F0h-1FFh of Bank 3 These locations are used for common access across banks. RP1:RP0 (STATUS<6:5>) Bank 11 3 (180h-1FFh) 10 2 (100h-17Fh) 01 1 (80h-FFh) 00 0 (00h-7Fh) |
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