PIC16C925-SSLASHCL datasheet(53/182 Pages) MICROCHIP

53 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 51

PIC16C925/926

7.0

TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It can be used as the PWM time-base for

the PWM mode of the CCP module. It can also be used

as a time-base for the Master mode SPI clock. The

TMR2 register is readable and writable, and is cleared

on any device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4,

1:16

(selected

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>)).

The Timer2 module has an 8-bit period register, PR2.

TMR2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

set during RESET.

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 7-1 shows the Timer2 control register.

7.1

Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (Power-on Reset, MCLR

Reset, or Watchdog Timer Reset)

TMR2 will not clear when T2CON is written.

7.2

Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module, which optionally uses

it to generate the shift clock.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Flag

TMR2 reg

Output(1)

RESET

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1

1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected by the

SSP Module as the source clock.

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