PIC16C925-SSLASHCL datasheet(52/182 Pages) MICROCHIP

52 / 182 page

PIC16C925/926

DS39544A-page 50

Preliminary

 2001 Microchip Technology Inc.

6.4

Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The oscilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 6-1 shows the capacitor

selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

TABLE 6-1:

CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

6.5

Resetting Timer1 Using the CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode, to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take pre-

cedence.

In this mode of operation, the CCPR1H:CCPR1L regis-

ters pair effectively become the period register for

Timer1.

6.6

Resetting of Timer1 Register Pair

(TMR1H:TMR1L)

TMR1H and TMR1L registers are not reset on a POR

or any other RESET, except by the CCP1 special event

trigger.

T1CON register is reset to 00h on a Power-on Reset.

In any other RESET, the register is unaffected.

6.7

Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 6-2:

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Osc Type

Freq

32 kHz

33 pF

100 kHz

15 pF

200 kHz

15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz

Epson C-001R32.768K-A

± 20 PPM

100 kHz

Epson C-2 100.00 KC-P

± 20 PPM

200 kHz

STD XTL 200.000 kHz

± 20 PPM

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components.

Note:

The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on

all other

RESETS

0Bh, 8Bh,

10Bh, 18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

PIR1

LCDIF

ADIF

—

SSPIF

CCP1IF

TMR2IF

TMR1IF

00-- 0000 00-- 0000

8Ch

PIE1

LCDIE

ADIE

—

SSPIE

CCP1IE

TMR2IE

TMR1IE

00-- 0000 00-- 0000

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

10h

T1CON

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by theTimer1 module.

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