PIC16C925-SSLASHCL datasheet(68/182 Pages) MICROCHIP

68 / 182 page

PIC16C925/926

DS39544A-page 66

Preliminary

 2001 Microchip Technology Inc.

9.2.2

ADDRESSING I2C DEVICES

There are two address formats. The simplest is the

7-bit address format with a R/W bit (Figure 9-7). The

more complex is the 10-bit address with a R/W bit

(Figure 9-8). For 10-bit address format, two bytes must

be transmitted with the first five bits specifying this to be

a 10-bit address.

FIGURE 9-7:

7-BIT ADDRESS FORMAT

FIGURE 9-8:

I2C 10-BIT ADDRESS

FORMAT

9.2.3

TRANSFER ACKNOWLEDGE

All data must be transmitted per byte, with no limit to

the number of bytes transmitted per data transfer. After

each byte, the slave-receiver generates an Acknowl-

edge bit (ACK) (see Figure 9-9). When a slave-receiver

doesn’t acknowledge the slave address or received

data, the master must abort the transfer. The slave

must leave SDA high so that the master can generate

the STOP condition (Figure 9-6).

FIGURE 9-9:

SLAVE-RECEIVER

ACKNOWLEDGE

If the master is receiving the data (master-receiver), it

generates an Acknowledge signal for each received

byte of data, except for the last byte. To signal the end

of data to the slave-transmitter, the master does not

generate an Acknowledge (Not Acknowledge). The

slave then releases the SDA line so the master can

generate the STOP condition. The master can also

generate the STOP condition during the Acknowledge

pulse for valid termination of data transfer.

If the slave needs to delay the transmission of the next

byte, holding the SCL line low will force the master into

a wait state. Data transfer continues when the slave

releases the SCL line. This allows the slave to move

the received data, or fetch the data it needs to transfer

before allowing the clock to start. This wait state tech-

nique can also be implemented at the bit level,

Figure 9-10. The slave will inherently stretch the clock

when it is a transmitter, but will not when it is a receiver.

The slave will have to clear the SSPCON<4> bit to

enable clock stretching when it is a receiver.

FIGURE 9-10:

DATA TRANSFER WAIT STATE

R/W ACK

Sent by

Slave

Slave Address

R/W

Read/Write pulse

MSb

LSb

START Condition

ACK

Acknowledge

S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

Sent by Slave

= 0 for Write

R/W

ACK

- START Condition

- Read/Write Pulse

- Acknowledge

Data

Output by

Transmitter

Data

Output by

Receiver

SCL from

Master

START

Condition

Clock Pulse for

Acknowledgment

Not Acknowledge

Acknowledge

• 89

SDA

SCL

START

Condition

Address

R/W

ACK

Wait

State

Data

ACK

MSB

Acknowledgment

Signal from Receiver

Acknowledgment

Signal from Receiver

Byte Complete

Interrupt with Receiver

Clock Line Held Low while

Interrupts are Serviced

STOP

Condition

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