PIC16C925-SSLASHCL datasheet(93/182 Pages) MICROCHIP

93 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 91

PIC16C925/926

11.2

LCD Interrupts

The LCD timing generation provides an interrupt that

defines the LCD frame timing. This interrupt can be

used to coordinate the writing of the pixel data with the

start of a new frame. Writing pixel data at the frame

boundary allows a visually crisp transition of the image.

This interrupt can also be used to synchronize external

events to the LCD. For example, the interface to an

external segment driver, such as a Microchip AY0438,

can be synchronized for segment data update to the

LCD frame.

A new frame is defined to begin at the leading edge of

the COM0 common signal. The interrupt will be set

immediately

after

the LCD

controller

completes

accessing all pixel data required for a frame. This will

occur at a fixed interval before the frame boundary

(TFINT), as shown in Figure 11-7. The LCD controller

will begin to access data for the next frame within the

interval from the interrupt to when the controller begins

to access data after the interrupt (TFWR). New data

must be written within TFWR, as this is when the LCD

controller will begin to access the data for the next

frame.

FIGURE 11-7:

EXAMPLE WAVEFORMS AND INTERRUPT TIMING

IN QUARTER-DUTY CYCLE DRIVE

COM0

COM1

COM2

COM3

3/3 V

2/3 V

1/3 V

0/3 V

3/3 V

2/3 V

1/3 V

0/3 V

3/3 V

2/3 V

1/3 V

0/3 V

3/3 V

2/3 V

1/3 V

0/3 V

Frame

Boundary

Frame

Boundary

1 Frame

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

TFINT

TFWR

TFWR = TFRAME/(LMUX1:LMUX0 + 1) + TCY/2

TFINT = (TFWR /2 - (2TCY + 40 ns))

→ minimum = 1.5(TFRAME/4) - (2TCY + 40ns)

(TFWR /2 - (1TCY + 40 ns))

→ maximum = 1.5(TFRAME/4) - (1TCY + 40 ns)

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