PIC16C925-SSLASHCL datasheet(73/182 Pages) MICROCHIP

73 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 71

PIC16C925/926

9.3.1.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

FIGURE 9-17:

I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

9.3.1.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and pin RC3/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then, pin RC3/SCK/SCL should be enabled by set-

ting bit CKP (SSPCON<4>). The master must monitor

the SCL pin prior to asserting another clock pulse. The

slave devices may be holding off the master by stretch-

ing the clock. The eight data bits are shifted out on the

falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 9-18).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the mas-

ter-receiver is latched on the rising edge of the ninth

SCL input pulse. If the SDA line was high (not ACK),

then the data transfer is complete. When the ACK is

latched by the slave, the slave logic is reset and the

slave then monitors for another occurrence of the

START bit. If the SDA line was low (ACK), the transmit

data must be loaded into the SSPBUF register, which

also

loads

the

SSPSR

Then,

RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 9-18:

I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

ACK

Transmitting Data

R/W = 1

Receiving Address

789

123

Cleared in software

SSPBUF is written in software

From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

Data in

sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written-to

before the CKP bit can be set)

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