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PIC16C925-S/CL датащи(PDF) 57 Page - Microchip Technology

номер детали PIC16C925-S/CL
подробное описание детали  64/68-Pin CMOS Microcontrollers with LCD Driver
PDF  182 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16C925-S/CL датащи(HTML) 57 Page - Microchip Technology

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 2001 Microchip Technology Inc.
Preliminary
DS39544A-page 55
PIC16C925/926
8.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, a compare interrupt is also generated.
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
QS
R
Output
Logic
Special event trigger will reset Timer1, but not
Set CCP1IF
PIR1<2>
Match
RC2/CCP1
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
set interrupt flag bit TMR1IF (PIR1<0>).
Note:
The “special event trigger” from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).



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