RM0319 datasheet(355/368 Pages) STMICROELECTRONICS

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RM0319

DMA controller (DMAC)

Doc ID 022640 Rev 3

355/368

36.3.6

How to program the DMAC for scatter/gather DMA

Write to memory all the LLIs for the complete DMA transfer (source address,

destination address, pointer to next LLI and control word for each LLI).

Choose a free DMA channel with the required priority (0 the highest to 7 the lowest).

Write the first LLI, previously written to memory (step 1), to the relevant DMA channel

in the DMAC, setting the corresponding registers (DMACCnSrcAddr,

DMACCnDestAddr, DMACCnLLI and DMACCnControl).

Write the DMA channel configuration information to the DMAC Configuration and set its

channel enable bit (E, bit [0]).

An interrupt can be generated at the end of each LLI setting the terminal count bit (I, bit

[31]) in the DMACCnControl register. Then, the interrupt request must be serviced and

the relevant bit of the IntTCClear field in the DMACIntTCClear register must be set to

clear the interrupt.

36.4

Interrupts

The DMAC allows to generate an interrupt to the ARM processor:

●

In case of a DMA error (assertion of an error response on the AHB during data transfer)

●

At the end of DMA transfer (terminal count reached 0)

The corresponding interrupt request signals are listed in Table 124. The combined

DMACINTR signal (generated as an OR function of the individual request signals,

DMACINTERR and DMACINTTC) can be useful in low performance system with a few

interrupt controller request inputs. As depicted in Figure 118, in this case only the

DMACINTR request signal coming from DMAC is directly connected to the interrupt

controller, but both the DMACIntErrStatus and the DMACIntTCStatus registers, in

conjunction with the DMACIntStatus register, must be read to find the actual source of the

interrupt.

Figure 118. DMAC-to-interrupt controller connection

In any case the error and terminal count interrupts can be masked at the DMAC-level by

programming the relevant bits (IE and ITC, respectively) on the relevant

DMACCnConfiguration channel register. In order to get interrupt status prior to masking, the

DMACRawIntErrStatus and the DMACRawIntTCStatus registers are provided by the DMAC.

DMAC

DMACINTR

nIRQ

nFIQ

Interrupt

controller

ARM

Processor

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