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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0319 датащи(PDF) 346 Page - STMicroelectronics |
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RM0319 датащи(HTML) 346 Page - STMicroelectronics |
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346 / 368 page  Vectored interrupt controller (VIC) RM0319 346/368 Doc ID 022640 Rev 3 33.4 Interrupts 33.4.1 Reducing interrupt latency The interrupt latency depends on the type of interrupt, see Table 122. To reduce interrupt latency, you can re-enable the IRQ interrupts in the processor after the ISR is entered, so the current ISR is interrupted, and the higher priority ISR is executed. The VIC then only enables a higher priority interrupt than the interrupt currently being serviced. If a higher priority interrupt goes active, the current ISR is interrupted and the higher-priority ISR is executed. Before the interrupt enable bits in the processor can be re-enabled, the LR and SPSR must be saved, preferably on a software stack. When the ISR is exited, you must disable the interrupts, reload the LR and SPSR, and write to the vector address register, VICVECTADDR. Table 122. Interrupt latency for different types of interrupts Event Worst case (cycles) FIQ IRQ IRQ (reduced latency) Interrupt synchronization 3 3 3 Worst case interrupt disable period 7 10 10 Entry to first instruction 2 2 2 Nesting, assuming single-state AHB - 10 - Load IRQ vector to PC - - 5 Total 122520 |
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