RM0319 datasheet(343/368 Pages) STMICROELECTRONICS

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RM0319

Vectored interrupt controller (VIC)

Doc ID 022640 Rev 3

343/368

Vectored interrupt controller (VIC)

This chapter focuses on VIC functionality and operation.

For technical details about the programmable registers related to the VIC, refer to the VIC

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

33.1

Overview

Acting as an interrupt controller, the VIC determines the source that is requesting service

and where its interrupt service routine (ISR) is loaded, doing that in hardware. In particular,

the VIC supplies the starting address, or vector address, of the ISR corresponding to the

highest priority requesting interrupt source.

Note:

Refer to Appendix A: Interrupt request table for a complete list of SPEAr320S external

interrupts.

33.2

Main features

●

Support for 32 standard interrupt sources

●

Generation of both fast interrupt request (FIQ) and interrupt request (IRQ), according to

ARM system operation. IRQ is used for general interrupts, whereas FIQ is intended for

fast, low-latency interrupt handling. In particular, using a single FIQ source at a time in

the system provides interrupt latency reduction, because the ISR can be directly

executed without determining the source of the interrupt.

●

Support for 16 vectored interrupts (IRQ only)

●

Hardware interrupt priority, where FIQ interrupt has the highest priority, followed by

vectored IRQ interrupts (from vector 0 to vector 15), and then non-vectored IRQ

interrupts with the lowest priority.

●

Interrupt masking

●

Interrupts request status and raw interrupt status (prior to masking)

●

Software interrupt generation

●

An AHB slave to connect to the CPU

The interrupt inputs must be level sensitive, active HIGH, and held asserted until the

interrupt service routine clears the interrupt. Edge-triggered interrupts are not compatible.

The interrupt inputs do not have to be synchronous to HCLK.

Note:

The VIC does not handle interrupt sources with transient behaviour.

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