RM0319 datasheet(296/368 Pages) STMICROELECTRONICS

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Security co-processor (C3)

RM0319

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Doc ID 022640 Rev 3

Security co-processor (C3)

This chapter focuses on C3 functionality and operation.

For technical details about the programmable registers related to the C3, refer to the C3

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

28.1

Overview

C3 is a DMA-based co-processor enabling the acceleration of data-driven computationally

expensive functions, such as: cryptography, pattern matching, signal processing, security

and network security applications. It can be used for other types of data intensive

applications as well.

It executes instruction flows generated by the host processor. After it has been set up by the

host, it runs in a completely autonomous way (DMA data in, data processing, DMA data

out), until the completion of all the requested operations.

28.2

Main features

●

C3 Hardware ID base address 0xFFFF_1000

●

Four instruction dispatchers

●

Four hardware accelerator channels with in/out FIFO inside

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64 KB of internal RAM for low latency accesses

●

Coupling/Chaining Module (internal cross-bar) for interchannel direct high-speed

communications, up to 8 paths

●

Highly programmable (instruction-driven) controller

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AMBA AHB 2.0 Master and Slave Interfaces

●

Scatter and Gather DMA engine

C3 has 8 slots for including channels (hardware accelerators). The channel configuration is

as follows:

Channel 0 - Empty

Channel 1 - Data Encryption Standard (DES and TripleDES)

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