RM0319 datasheet(194/368 Pages) STMICROELECTRONICS

194 / 368 page

Controller area network ports (CAN)

RM0319

194/368

Doc ID 022640 Rev 3

required. For communication on a CAN network, individual message objects are configured.

The message objects and identifier masks for acceptance filtering of received messages are

stored in the Message RAM. All functions concerning the handling of messages are

implemented in the Message Handler. Those functions are the acceptance filtering, the

transfer of messages between the CAN core and the message RAM, and the handling of

transmission requests as well as the generation of the module interrupt. The register set of

the CAN can be accessed directly by an external CPU via the module interface. These

registers are used to control/configure the CAN Core and the message handler and to

access the message RAM.

As shown in Figure 66: CAN controller block diagram, these are the main CAN core

interfaces:

●

CAN core: this is a CAN Protocol Controller and Rx/Tx Shift register for serial/parallel

conversion of messages.

●

Message RAM: Stores message objects and Identifier Masks.

●

Registers: All registers used to control and configure the CAN module

●

Message handler state machine: this is the state machine that controls the data

transfer between the Rx/Tx Shift register of the CAN core and the Message RAM as

well as the generation of interrupts as programmed in the control and configuration

registers. See also: Section 15.3.1.

●

Module interface: Interfaces to the AMBA APB bus from ARM

15.3.1

Message handler state machine

The message handler controls the data transfer between the Rx/Tx Shift register of the CAN

Core, the Message RAM and the IFx registers.

The Message Handler FSM controls the following functions:

●

Data transfer from IFx register to the message RAM

●

Data transfer from message RAM to the IFx registers

●

Data transfer from Shift register to the message RAM

●

Data transfer from message RAM to Shift register

●

Data transfer from Shift register to the acceptance filtering unit

●

Scanning of message RAM for a matching message object

●

Handling of TxRqst flags

●

Handling of interrupts

Data transfer from/to message RAM

When the CPU initiates a data transfer between the IFx registers and the message RAM,

the message handler sets the Busy bit in the respective Command register to ‘1’. After the

transfer has been completed, the Busy bit is set back to ‘0’ (see Figure 67).

The respective Command Mask register specifies whether a complete message object or

only parts of it will be transferred. Due to the structure of the message RAM it is not possible

to write single bits/bytes of one message object, it is always necessary to write a complete

message object into the message RAM. Therefore, the data transfer from the IFx registers

to the message RAM requires a read-modify-write cycle. First, the parts of the message

object that are not to be changed are read from the Message RAM, and then the complete

contents of the Message Buffer registers are into the message object.

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