PM0056 datasheet(143/156 Pages) STMICROELECTRONICS

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DocID15491 Rev 5

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PM0056

Core peripherals

Bit 19

NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions:

0: No usage fault caused by attempting to access a coprocessor

1: the processor has attempted to access a coprocessor.

Bit 18

INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:

When this bit is set to 1, the PC value stacked for the exception return points to the instruction

that tried to perform the illegal load of the PC.

0: No invalid PC load usage fault

1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an

invalid context, or an invalid EXC_RETURN value.

Bit 17

INVSTATE: Invalid state usage fault:

When this bit is set to 1, the PC value stacked for the exception return points to the instruction

that attempted the illegal use of the EPSR.

This bit is not set to 1 if an undefined instruction uses the EPSR.

0: No invalid state usage fault

1: The processor has attempted to execute an instruction that makes illegal use of the

EPSR.

Bit 16

UNDEFINSTR: Undefined instruction usage fault:

When this bit is set to 1, the PC value stacked for the exception return points to the undefined

instruction.

An undefined instruction is an instruction that the processor cannot decode.

0: No undefined instruction usage fault

1: The processor has attempted to execute an undefined instruction.

Bit 15

BFARVALID: Bus Fault Address Register (BFAR) valid flag:

The processor sets this bit to 1 after a bus fault where the address is known. Other faults can

set this bit to 0, such as a memory management fault occurring later.

If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler

must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler

whose BFAR value has been overwritten.

0: Value in BFAR is not a valid fault address

1: BFAR holds a valid fault address.

Bits 14:13

Reserved, must be kept cleared

Bit 12

STKERR: Bus fault on stacking for exception entry

When the processor sets this bit to 1, the SP is still adjusted but the values in the context area

on the stack might be incorrect. The processor does not write a fault address to the BFAR.

0: No stacking fault

1: Stacking for an exception entry has caused one or more bus faults.

Bit 11

UNSTKERR: Bus fault on unstacking for a return from exception

This fault is chained to the handler. This means that when the processor sets this bit to 1, the

original return stack is still present. The processor does not adjust the SP from the failing

return, does not performed a new save, and does not write a fault address to the BFAR.

0: No unstacking fault

1: Unstack for an exception return has caused one or more bus faults.

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