PM0056 datasheet(140/156 Pages) STMICROELECTRONICS

140 / 156 page

Core peripherals

PM0056

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DocID15491 Rev 5

System handler priority register 3 (

SCB_SHPR3)

Address: 0xE000 ED20

Reset value: 0x0000 0000

Required privilege: Privileged

4.4.9

System handler control and state register (SCB_SHCSR)

Address offset: 0x24

Reset value: 0x0000 0000

Required privilege: Privileged

The SHCSR enables the system handlers, and indicates:

•

The pending status of the bus fault, memory management fault, and SVC exceptions

•

The active status of the system handlers.

If you disable a system handler and the corresponding fault occurs, the processor treats the

fault as a hard fault.

You can write to this register to change the pending or active status of system exceptions.

An OS kernel can write to the active bits to perform a context switch that changes the

current exception type.

•

Software that changes the value of an active bit in this register without correct

adjustment to the stacked content can cause the processor to generate a fault

exception. Ensure software that writes to this register retains and subsequently

restores the current active status.

•

After you have enabled the system handlers, if you have to change the value of a bit in

this register you must use a read-modify-write procedure to ensure that you change

only the required bit.

3029

PRI_15[7:4]

PRI_15[3:0]

PRI_14[7:4]

PRI_14[3:0]

Reserved

Bits 31:24

PRI_15[7:0]: Priority of system handler 15, SysTick exception

Bits 23:16

PRI_14[7:0]: Priority of system handler 14, PendSV

Bits 15:0

Reserved, must be kept cleared

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