PM0056 datasheet(138/156 Pages) STMICROELECTRONICS

138 / 156 page

Core peripherals

PM0056

138/156

DocID15491 Rev 5

4.4.8

System handler priority registers (SHPRx)

The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that

have configurable priority.

SHPR1-SHPR3 are byte accessible.

The system fault handlers and the priority field and register for each handler are:

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field,

and bits[3:0] read as zero and ignore writes.

Bit 3

UNALIGN_ TRP

Enables unaligned access traps:

0: Do not trap unaligned halfword and word accesses

1: Trap unaligned halfword and word accesses.

If this bit is set to 1, an unaligned access generates a usage fault.

Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether

UNALIGN_TRP is set to 1.

Bit 2

Reserved, must be kept cleared

Bit 1

USERSETMPEND

Enables unprivileged software access to the STIR, see Software trigger interrupt register

(NVIC_STIR) on page 126:

0: Disable

1: Enable.

Bit 0

NONBASETHRDENA

Configures how the processor enters Thread mode.

0: Processor can enter Thread mode only when no exception is active.

1: Processor can enter Thread mode from any level under the control of an EXC_RETURN

value, see Exception return on page 39.

Table 46. System fault handler priority fields

Handler

Field

Memory management fault

PRI_4

System handler priority register 1 (SCB_SHPR1)

Bus fault

PRI_5

Usage fault

PRI_6

SVCall

PRI_11

System handler priority register 2 (SCB_SHPR2) on

page 139

PendSV

PRI_14

System handler priority register 3 (SCB_SHPR3) on

page 140

SysTick

PRI_15

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