PM0056 datasheet(106/156 Pages) STMICROELECTRONICS

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Core peripherals

PM0056

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The Cortex-M3 MPU memory map is unified. This means instruction accesses and data

accesses have same region settings.

If a program accesses a memory location that is prohibited by the MPU, the processor

generates a memory management fault. This causes a fault exception, and might cause

termination of the process in an OS environment.

In an OS environment, the kernel can update the MPU region setting dynamically based on

the process to be executed. Typically, an embedded OS uses the MPU for memory

protection.

Configuration of MPU regions is based on memory types, see Section 2.2.1: Memory

regions, types and attributes on page 25.

Table 34 shows the possible MPU region attributes.

4.2.1

MPU access permission attributes

This section describes the MPU access permission attributes. The access permission bits,

TEX, C, B, S, AP, and XN, of the MPU_RASR register, control access to the corresponding

memory region. If an access is made to an area of memory without the required

permissions, then the MPU generates a permission fault.

Table 35 shows the encodings for the TEX, C, B, and S access permission bits.

Table 34. Memory attributes summary

Memory type

Shareability

Other attributes

Description

Strongly- ordered

All accesses to Strongly-ordered

memory occur in program order. All

Strongly-ordered regions are

assumed to be shared.

Device

Shared

Memory-mapped peripherals that

several processors share.

Non-shared

Memory-mapped peripherals that

only a single processor uses.

Normal

Shared

Non-cacheable

Write-through

Cacheable

Write-back

Cacheable

Normal memory that is shared

between several processors.

Non-shared

Non-cacheable

Write-through

Cacheable

Write-back

Cacheable

Normal memory that only a single

processor uses.

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