PIC18F242 datasheet(129/332 Pages) MICROCHIP

129 / 332 page

DS39564C-page 127

PIC18FXX2

SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit (Transmit mode only)

= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow

(must be cleared in software).

= No overflow

Note:

In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

SSPEN: Synchronous Serial Port Enable bit

= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

bit 4

CKP: Clock Polarity Select bit

= IDLE state for clock is a high level

= IDLE state for clock is a low level

bit 3-0

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101

= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100

= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011

= SPI Master mode, clock = TMR2 output/2

0010

= SPI Master mode, clock = FOSC/64

0001

= SPI Master mode, clock = FOSC/16

0000

= SPI Master mode, clock = FOSC/4

Note:

Bit combinations not specifically listed here are either reserved, or implemented in

I2C mode only.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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