PIC18F242 datasheet(95/332 Pages) MICROCHIP

95 / 332 page

DS39564C-page 93

PIC18FXX2

9.3

PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISC bit (= 0) will

make the corresponding PORTC pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

PORTC is multiplexed with several peripheral functions

(Table 9-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

RC1 is normally configured by configuration bit,

CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = ’1’).

EXAMPLE 9-3:

INITIALIZING PORTC

FIGURE 9-7:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISC

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

Data Bus

WR LATC or

WR TRISC

RD TRISC

Peripheral Data Out

RD PORTC

Peripheral Data In

WR PORTC

RD LATC

Peripheral Output

Schmitt

Port/Peripheral Select(2)

Enable(3)

VSS

VDD

I/O pin(1)

Note 1:

I/O pins have diode protection to VDD and VSS.

Port/Peripheral Select signal selects between port data (input) and peripheral output.

Peripheral Output Enable is only active if peripheral select is active.

Data Latch

TRIS Latch

Trigger

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