PIC18F242 datasheet(44/332 Pages) MICROCHIP

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PIC18FXX2

DS39564C-page 42

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

allowing up to 4096 bytes of data memory. Figure 4-6

and Figure 4-7 show the data memory organization for

the PIC18FXX2 devices.

The data memory map is divided into as many as 16

banks that contain 256 bytes each. The lower 4 bits of

the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

The data memory contains Special Function Registers

(SFR) and General Purpose Registers (GPR). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(0xFFF) and extend downwards. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ’0’s.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the Data Memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFF instruction. The

MOVFF

instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

provides a detailed description of the Access RAM.

4.9.1

GENERAL PURPOSE REGISTER

FILE

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

operation

indirect

addressing

shown

Section 4.12.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. The top half of Bank 15 (0xF80 to 0xFFF)

contains SFRs. All other banks of data memory contain

GPR registers, starting with Bank 0.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-1 and Table 4-2.

The SFRs can be classified into two sets; those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The

SFRs

are

typically

distributed

among

the

peripherals whose functions they control.

The unused SFR locations will be unimplemented and

read as '0's. See Table 4-1 for addresses for the SFRs.

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