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PIC18F242 датащи(PDF) 84 Page - Microchip Technology

номер детали PIC18F242
подробное описание детали  High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D
PDF  332 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F242 датащи(HTML) 84 Page - Microchip Technology

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PIC18FXX2
DS39564C-page 82
© 2006 Microchip Technology Inc.
8.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Priority Registers (IPR1, IPR2). The operation of
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP(1): Parallel Slave Port Read/Write Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1
= High priority
0
= Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1
= High priority
0
= Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit set.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown



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