PIC18F242 datasheet(62/332 Pages) MICROCHIP

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PIC18FXX2

DS39564C-page 60

5.4

Erasing FLASH Program memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control can larger blocks of program memory be

bulk erased. Word erase in the FLASH array is not

supported.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the FLASH pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal

FLASH. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

5.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

Load table pointer with address of row being

erased.

Set EEPGD bit to point to program memory,

clear CFGS bit to access program memory, set

WREN bit to enable writes, and set FREE bit to

enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write AAh to EECON2.

Set the WR bit. This will begin the row erase

cycle.

The CPU will stall for duration of the erase

(about 2 ms using internal timer).

Re-enable interrupts.

EXAMPLE 5-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

ERASE_ROW

BSF

EECON1,EEPGD

; point to FLASH program memory

BCF

EECON1,CFGS

; access FLASH program memory

BSF

EECON1,WREN

; enable write to memory

BSF

EECON1,FREE

; enable Row Erase operation

BCF

INTCON,GIE

; disable interrupts

MOVLW

55h

Required

MOVWF

EECON2

; write 55h

Sequence

MOVLW

AAh

MOVWF

EECON2

; write AAh

BSF

EECON1,WR

; start erase (CPU stall)

BSF

INTCON,GIE

; re-enable interrupts

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