PIC18F242 datasheet(24/332 Pages) MICROCHIP

24 / 332 page

PIC18FXX2

DS39564C-page 22

2.6.2

OSCILLATOR TRANSITIONS

The PIC18FXX2 devices contain circuitry to prevent

“glitches” when switching between oscillator sources.

Essentially, the circuitry waits for eight rising edges of

the clock source that the processor is switching to. This

ensures that the new clock source is stable and that its

pulse width will not be less than the shortest pulse

width of the two clock sources.

A timing diagram indicating the transition from the main

oscillator to the Timer1 oscillator is shown in

Figure 2-8. The Timer1 oscillator is assumed to be run-

ning all the time. After the SCS bit is set, the processor

is frozen at the next occurring Q1 cycle. After eight syn-

chronization cycles are counted from the Timer1 oscil-

lator, operation resumes. No additional delays are

required after the synchronization cycles.

FIGURE 2-8:

TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

If the main oscillator is configured for an external crys-

tal (HS, XT, LP), then the transition will take place after

an oscillator start-up time (TOST) has occurred. A timing

diagram, indicating the transition from the Timer1 oscil-

lator to the main oscillator for HS, XT and LP modes, is

shown in Figure 2-9.

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

OSC1

Internal

SCS

(OSCCON<0>)

Program

PC + 2

Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.

T1OSI

PC + 4

Tscs

Clock

Counter

System

TDLY

TT1P

TOSC

5678

OSC1

Internal System

SCS

(OSCCON<0>)

Program Counter

PC + 2

Note 1: TOST = 1024 TOSC (drawing not to scale).

T1OSI

Clock

OSC2

TOST

PC + 6

TT1P

TOSC

TSCS

567

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