PIC18F242 datasheet(59/332 Pages) MICROCHIP

59 / 332 page

DS39564C-page 57

PIC18FXX2

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: FLASH Program or Data EEPROM Memory Select bit

= Access FLASH Program memory

= Access Data EEPROM memory

bit 6

CFGS: FLASH Program/Data EE or Configuration Select bit

= Access Configuration registers

= Access FLASH Program or Data EEPROM memory

bit 5

Unimplemented: Read as '0'

bit 4

FREE: FLASH Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write only

bit 3

WRERR: FLASH Program/Data EE Error Flag bit

= A write operation is prematurely terminated

(any RESET during self-timed programming in normal operation)

= The write operation completed

Note:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

WREN: FLASH Program/Data EE Write Enable bit

= Allows write cycles

= Inhibits write to the EEPROM

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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