PIC18F242 datasheet(63/332 Pages) MICROCHIP

63 / 332 page

DS39564C-page 61

PIC18FXX2

5.5

Writing to FLASH Program

Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

Table Writes are used internally to load the holding reg-

isters needed to program the FLASH memory. There

are 8 holding registers used by the Table Writes for

programming.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the Table Write

operations will essentially be short writes, because only

the holding registers are written. At the end of updating

8 registers, the EECON1 register must be written to, to

start the programming operation with a long write.

The long write is necessary for programming the inter-

nal FLASH. Instruction execution is halted while in a

long write cycle. The long write will be terminated by

the internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

FIGURE 5-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

5.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

Read 64 bytes into RAM.

Update data values in RAM as necessary.

Load Table Pointer with address being erased.

Do the row erase procedure.

Load Table Pointer with address of first byte

being written.

Write the first 8 bytes into the holding registers

with auto-increment (TBLWT*+ or TBLWT+*).

Set EEPGD bit to point to program memory,

clear the CFGS bit to access program memory,

and set WREN to enable byte writes.

Disable interrupts.

Write 55h to EECON2.

10. Write AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

13. Re-enable interrupts.

14. Repeat steps 6-14 seven times, to write

64 bytes.

15. Verify the memory (Table Read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 5-3.

Holding Register

TABLAT

Holding Register

TBLPTR = xxxxx7

Holding Register

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx0

Write Register

TBLPTR = xxxxx2

Program Memory

Note:

Before setting the WR bit, the table pointer

address needs to be within the intended

address range of the 8 bytes in the holding

registers.

PIC18F242 датащи(PDF) 63 Page - Microchip Technology

PIC18F242 датащи(HTML) 63 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL