PIC18F242 datasheet(89/332 Pages) MICROCHIP

89 / 332 page

DS39564C-page 87

PIC18FXX2

9.0

I/O PORTS

Depending on the device selected, there are either five

ports or three ports available. Some pins of the I/O

ports are multiplexed with an alternate function from

the peripheral features on the device. In general, when

a peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The data latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

9.1

PORTA, TRISA and LATA

Registers

PORTA is a 7-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The RA4/

T0CKI pin is a Schmitt Trigger input and an open drain

output. All other RA port pins have TTL input levels and

full CMOS output drivers.

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

Register1).

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 9-1:

INITIALIZING PORTA

FIGURE 9-1:

BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

Note:

On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA6 and RA4 are configured as

digital inputs.

CLRF PORTA

; Initialize PORTA by

; clearing output

; data latches

CLRF LATA

; Alternate method

; to clear output

; data latches

MOVLW 0x07

; Configure A/D

MOVWF ADCON1

; for digital inputs

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

Data

Bus

WR LATA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

VSS

VDD

I/O pin(1)

Note 1:

I/O pins have protection diodes to VDD and VSS.

Analog

Input

Mode

TTL

Input

Buffer

To A/D Converter and LVD Modules

RD LATA

PORTA

SS Input (RA5 only)

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