PIC18F242 datasheet(97/332 Pages) MICROCHIP

97 / 332 page

DS39564C-page 95

PIC18FXX2

9.4

PORTD, TRISD and LATD

Registers

This section is applicable only to the PIC18F4X2

devices.

PORTD is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISD bit (= 0) will

make the corresponding PORTD pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL. See Section 9.6 for additional information on

the Parallel Slave Port (PSP).

EXAMPLE 9-4:

INITIALIZING PORTD

FIGURE 9-8:

PORTD BLOCK DIAGRAM

IN I/O PORT MODE

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

Data

Bus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATD

PORTD

Note 1:

I/O pins have diode protection to VDD and VSS.

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