PIC18F242 datasheet(121/332 Pages) MICROCHIP

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DS39564C-page 119

PIC18FXX2

14.3

Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 or TMR3 registers when an

event occurs on pin RC2/CCP1. An event is defined as

one of the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set; it must be

cleared in software. If another capture occurs before the

value in register CCPR1 is read, the old captured value

is overwritten by the new captured value.

14.3.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

14.3.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(either Timer1 and/or Timer3) must be running in Timer

mode or Synchronized Counter mode. In Asynchro-

nous Counter mode, the capture operation may not

work. The timer to be used with each CCP module is

selected in the T3CON register.

14.3.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in Operating mode.

14.3.4

CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

RESET will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 14-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 14-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 14-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note:

If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

CLRF

CCP1CON, F ; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP1CON

; Load CCP1CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

TMR3

Enable

Q’s

CCP1CON<3:0>

CCP1 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1

Enable

T3CCP2

CCPR2H

CCPR2L

TMR1H

TMR1L

Set Flag bit CCP2IF

TMR3

Enable

Q’s

CCP2CON<3:0>

CCP2 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

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