PIC18F242 datasheet(117/332 Pages) MICROCHIP

117 / 332 page

DS39564C-page 115

PIC18FXX2

13.2

Timer1 Oscillator

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN (T1CON<3>) bit. The oscillator is a low

power oscillator rated up to 200 KHz. See Section 11.0

for further details.

13.3

Timer3 Interrupt

The TMR3 Register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR3 Interrupt, if enabled, is generated on overflow,

which is

latched in interrupt

flag

bit, TMR3IF

(PIR2<1>). This interrupt can be enabled/disabled by

setting/clearing TMR3 interrupt enable bit, TMR3IE

(PIE2<1>).

13.4

Resetting Timer3 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer3.

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer3 is running in Asynchronous Counter mode,

this RESET operation may not work. In the event that a

write to Timer3 coincides with a special event trigger

from CCP1, the write will take precedence. In this mode

of operation, the CCPR1H:CCPR1L registers pair

effectively becomes the period register for Timer3.

TABLE 13-1:

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note:

The special event triggers from the CCP

module will not set interrupt flag bit,

TMR3IF (PIR1<0>).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR2

—

EEIF

BCLIF

LVDIF

TMR3IF

CCP2IF

---0 0000

PIE2

—

EEIE

BCLIE

LVDIE

TMR3IE

CCP2IE

---0 0000

IPR2

—

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP

---1 1111

TMR3L

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

xxxx xxxx

uuuu uuuu

TMR3H

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx

uuuu uuuu

T1CON

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN

T1SYNC

TMR1CS

TMR1ON 0-00 0000

u-uu uuuu

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON

0000 0000

uuuu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

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