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AD9789

Rev. A | Page 29 of 76

SPI REGISTER DESCRIPTIONS

Table 12. SPI Control Register (Address 0x00)

Bit

Bit Name

Description

SDIO_DIR

This bit configures the SDIO pin as an input-only pin or as a bidirectional input/output pin. Both choices conform

to the SPI standard.

0 = input only.

1 = bidirectional (input/output).

LSBFIRST

This bit configures the SPI interface for MSB first or LSB first mode. Both choices conform to the SPI standard.

0 = MSB first.

1 = LSB first.

RESET

When set to 1, this bit resets the part. After the part is reset, 0 is written to this bit on the next cycle.

0 = no reset.

1 = software reset.

LNG_INST

This bit sets the SPI to long instruction mode; 1 is the only valid value.

[3:0]

These bits should mirror Bits[7:4]. Bit 3 should mirror Bit 4, Bit 2 should mirror Bit 5, Bit 1 should mirror Bit 6, and

Bit 0 should mirror Bit 7.

Table 13. Saturation Counter Register (Address 0x01)

Bit

Bit Name

Description

[7:0]

SATCNT[7:0]

This read-only register contains the saturation counter. This register reflects the number of samples at the output of

the SUMSCALE gain block that overrange the datapath and are digitally clipped. The count is cleared by writing

a 1 to Register 0x04, Bit 1.

Table 14. Parity Counter Register (Address 0x02)

Bit

Bit Name

Description

[7:0]

PARCNT[7:0]

This read-only register contains the input data parity error counter. The count is cleared by writing a 1 to

Table 15. Interrupt Enable Register (Address 0x03)

Bit

Name

Description

PARERR

Setting this bit to 1 enables a PARERR flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 7 being set in Register 0x04 and the IRQ pin going low.

BISTDONE

Setting this bit to 1 enables a BISTDONE flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 6 being set in Register 0x04 and the IRQ pin going low.

PARMSET

Setting this bit to 1 enables a PARMS_SET flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 5 being set in Register 0x04 and the IRQ pin going low.

PARMCLR

Setting this bit to 1 enables a PARMS_CLR flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 4 being set in Register 0x04 and the IRQ pin going low.

LOCKACQ

Setting this bit to 1 enables a LOCKACQ flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 3 being set in Register 0x04 and the IRQ pin going low.

LOCKLOST

Setting this bit to 1 enables a LOCKLOST flag to generate an interrupt request. Generating an interrupt request

results in Interrupt Bit 2 being set in Register 0x04 and the IRQ pin going low.

SATERR

Setting this bit to 1 enables a SATERR (overflow into 16× interpolator) flag to generate an interrupt request.

Generating an interrupt request results in Interrupt Bit 1 being set in Register 0x04 and the IRQ pin going low.

Reserved

Reserved.

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