AD9789BBCZ datasheet(35/76 Pages) AD

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AD9789

Rev. A | Page 35 of 76

Table 34. Internal Clock Phase Adjust Register (Address 0x23)

Bit

Bit Name

Description

[7:4]

DSCPHZ[3:0]

The data sampling clock (DSC) is an internal clock that is used to sample the input data. This clock can occur on

1 of 16 phases to optimize the setup and hold timing of the data interface.

Setting

Selected Phase

0000

Earliest clock phase

0001

Second earliest clock phase that occurs 1/16 of a DSC cycle later

…

1111

Last available clock phase

[3:0]

SNCPHZ[3:0]

The synchronization clock (SNC) is an internal clock that is used to synchronize the digital datapath clock with

the DAC clock. This clock can occur on 1 of 16 phases to optimize the DAC-to-datapath timing.

Setting

Selected Phase

0000

Earliest clock phase

0001

Second earliest clock phase that occurs 1/16 of a DSC cycle later

…

1111

Last available clock phase

Table 35. Parameter Update Register (Address 0x24)

Bit

Name

Description

PARMNEW

This bit must transition from 0 to 1 for changes to Register 0x22 and Register 0x23 to take effect. Assuming that

this bit was previously set to 0, writing a 1 to this bit causes the readback value of the bit to reflect the state of

the chip. (The state of the chip is updated very quickly; for this reason, users with slow SPI implementations may

never read back a 0 after an update.)

0 = values have not been updated.

1 = values have been updated.

[6:0]

Reserved

Reserved.

Table 36. Channel Gain Registers (Address 0x25 to Address 0x28)

Address

Bit Name

Description

0x25

0x26

0x27

0x28

Channel 0 gain

Channel 1 gain

Channel 2 gain

Channel 3 gain

CHAN0GAIN[7:0]

CHAN1GAIN[7:0]

CHAN2GAIN[7:0]

CHAN3GAIN[7:0]

These registers configure a value for the 1.7 multiplier applied to each individual

channel just prior to the SUMSCALE block. The range of the channel gain is 0 to

1.9921875 with a step size of 0.0078125. To mute an individual channel, set the

scale factor to 0.

Setting

Channel Gain

00000000

00000001

0.0078125

…

11111111

1.9921875

Table 37. Spectrum Shaping Register (Address 0x29)

Bit

Name

Description

[7:1]

Reserved

Reserved.

SPEC_INV

Setting this bit to 1 spectrally inverts the signal, effectively multiplying the Q data by −1.

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