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AD9789BBCZ датащи(PDF) 31 Page - Analog Devices

номер детали AD9789BBCZ
подробное описание детали  14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
PDF  76 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9789BBCZ датащи(HTML) 31 Page - Analog Devices

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AD9789
Rev. A | Page 31 of 76
Table 19. QAM/SRRC Configuration Register (Address 0x07)
Table 20. Summing Node Scalar Register (Address 0x08)
Table 21. Input Scalar Register (Address 0x09)
Bit
Bit Name
Description
[7:6]
Reserved
Reserved.
[5:4]
ALPHA[1:0]
These bits set the SRRC filter alpha.
Setting
Alpha Filter
00
0.12
01
0.18
10
0.15
11
0.13
3
Reserved
Reserved.
[2:0]
MAPPING[2:0]
These bits set the QAM encoding.
Setting
QAM Encoding
000
DOCSIS 64-QAM
001
DOCSIS 256-QAM
010
DVB-C 16-QAM
011
DVB-C 32-QAM
100
DVB-C 64-QAM
101
DVB-C 128-QAM
110
DVB-C 256-QAM
111
Unused
Bit
Bit Name
Description
[7:0]
SUMSCALE[7:0]
This register sets the value of the 2.6 multiplier that is applied to the output of the channel summing node.
Setting
2.6 Multiplier
00000000
0
00000001
0.015625
00000010
0.03125
…
…
00001101
0.203125 (default)
…
…
11111110
3.96875
11111111
3.984375
Bit
Bit Name
Description
[7:0]
INSCALE[7:0]
This register sets the value of the 3.5 multiplier that is applied to the input data. This scaling block is in parallel
with the QAM encoder block and is used when the QAM encoder block is bypassed.
Setting
3.5 Multiplier
00000000
0
00000001
0.03125
00000010
0.0625
…
…
00100000
1 (default)
…
…
11111110
7.9375
11111111
7.96875



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