AD9789BBCZ datasheet(5/76 Pages) AD

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AD9789

Rev. A | Page 5 of 76

DIGITAL SPECIFICATIONS

AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, LVDS drivers and receivers

are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

CMOS DATA INPUTS (D[31:0], P0, P1)

Input Voltage High, VIH

2.0

3.3

Input Voltage Low, VIL

0.8

Input Current High, IIH

−10

+10

μA

Input Current Low, IIL

−10

+10

μA

Input Capacitance

Setup Time, CMOS Data Input to CMOS_DCO1

5.3

Hold Time, CMOS Data Input to CMOS_DCO1

−1.4

CMOS OUTPUTS (CMOS_FS, CMOS_DCO)

Output Voltage High, VOH

2.4

3.3

Output Voltage Low, VOL

0.4

Output Current High, IOH

Output Current Low, IOL

Maximum Clock Rate (CMOS_DCO)

150

MHz

CMOS_DCO to CMOS_FS Delay

0.28

0.85

LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN)

Input Voltage Range, VIA or VIB

825

1575

Input Differential Threshold, VIDTH

−100

+100

Input Differential Hysteresis, VIDTHH, VIDTHL

Input Differential Input Impedance, RIN

120

Maximum LVDS Input Rate

150

MSPS

Setup Time, LVDS Differential Input Data to Differential DCOx2

1.41

Hold Time, LVDS Differential Input Data to Differential DCOx2

0.24

LVDS OUTPUTS (DCOP, DCON, FSP, FSN)

DCOP, FSP = VOA; DCON, FSN = VOB; 100 Ω Termination

Output Voltage High, VOA or VOB

1375

Output Voltage Low, VOA or VOB

1025

Output Differential Voltage, |VOD|

150

200

250

Output Offset Voltage, VOS

1150

1250

Output Impedance, Single Ended, RO

140

RO Mismatch Between A and B, ∆RO

Change in |VOD| Between 0 and 1, |∆VOD|

Change in VOS Between 0 and 1, ∆VOS

Output Current—Driver Shorted to Ground, ISA, ISB

Output Current—Drivers Shorted Together, ISAB

Power-Off Output Leakage, |IXA|, |IXB|

Maximum Clock Rate (DCOP, DCON)

150

MHz

DCOx to FSx Delay

0.12

0.37

DAC CLOCK INPUT (CLKP, CLKN)3

Differential Peak Voltage

1.4

1.8

Common-Mode Voltage

900

DAC Clock Rate

2400

MHz

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (fSCLK, 1/tSCLK)

MHz

Minimum Pulse Width High, tPWH

Minimum Pulse Width Low, tPWL

Minimum SDIO and CS to SCLK Setup, tDS

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