AD9789BBCZ datasheet(61/76 Pages) AD

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AD9789

Rev. A | Page 61 of 76

INTERRUPT REQUESTS

Operating the Mu Controller in Manual Mode

The following interrupt (IRQ) requests can be used for additional

information and verification of the status of various functional

blocks:

In manual mode, the user must sweep through all the mu delay

values and record the phase value at each value of MUDLY as

shown in Figure 118. Every time that the MUDLY value is

stepped, the MUSAMP bit must be toggled from low to high

to read the corresponding phase for the specified mu delay line

value. It is not possible to keep read high and continuously read

back the phase value. As with auto mode, the optimal ac perfor-

mance occurs at a positive slope and a phase of 14; therefore,

when the curve is complete, choose the MUDLY value that

corresponds to this condition and write that value to the

MUDLY[8:0] bits (Register 0x39[7] and Register 0x3A).

•

PARERR—triggered when one or more parity errors

occurs on the data bus

•

PARMSET—triggered when PARMNEW is set and

internally registered

•

PARMCLR—triggered when PARMNEW is cleared and

internally registered

•

LOCKACQ—triggered when the mu controller is locked to

the user-defined phase

Calculating Mu Delay Line Step Size

•

LOCKLOST—triggered when the mu controller loses lock

(if the LOCKACQ bit was previously set)

Stepping through all of the mu delay line values and plotting

mu phase vs. mu delay not only allows the user to find the

optimal mu delay value, but can also allow the user to determine

the mu delay line step size. To calculate the step size, take one

full cycle of the mu phase curve and divide the period of the

DAC clock by this delta. From Figure 118, the two transition

points are approximately 56 and 270, providing a delta of approx-

imately 214 steps. Therefore, the mu delay line step size would

be approximately 2 ps/step, as shown in the following equation:

•

SATERR—triggered when one or more saturation errors

occurs

Each IRQ is enabled using the enable bits in the interrupt

enable register, Register 0x03. The status of the IRQ can be

measured in one of the following ways: via the SPI bits found in

the interrupt status/clear register (Register 0x04) or using the

IRQ pin (Pin P2).

If the pin is used to determine that an interrupt has occurred,

it is necessary to check Register 0x04 to determine which bit

caused the interrupt because the pin indicates only that an

interrupt has occurred. To clear an IRQ, it is necessary to write

a 1 to the bit in Register 0x04 that corresponds to the interrupt.

214

GHz

⎟

⎠

⎞

⎜

⎝

⎛

If the mu controller is enabled, this value allows the user to

calculate (in picoseconds) how much drift is in their system

with respect to the DAC clock period over temperature.

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