AD9789BBCZ datasheet(23/76 Pages) AD

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AD9789

Rev. A | Page 23 of 76

SERIAL CONTROL PORT

The AD9789 serial control port is a flexible, synchronous serial

communications port that allows an easy interface to many

industry-standard microcontrollers and microprocessors. The

AD9789 serial control port is compatible with most synchronous

transfer formats, including both the Motorola SPI® and Intel® SSR

protocols. The serial control port allows read/write access to all

registers that configure the AD9789. Single- or multiple-byte

transfers are supported, as well as MSB first or LSB first transfer

formats. The AD9789 serial control port can be configured for a

single bidirectional I/O pin (SDIO only) or for two unidirectional

I/O pins (SDIO/SDO). By default, the AD9789 is in unidirectional

long instruction mode (long instruction mode is the only

instruction mode supported).

SERIAL CONTROL PORT PIN DESCRIPTIONS

The SCLK (serial clock) pin is the serial shift clock. This pin is

an input. SCLK is used to synchronize serial control port reads

and writes. Write data bits are registered on the rising edge of

this clock, and read data bits are registered on the falling edge.

This pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin that acts

as an input only (unidirectional mode) or as both an input and

an output (bidirectional mode). The AD9789 defaults to the

unidirectional I/O mode (Register 0x00[7] = 0).

The SDO (serial data output) pin is used only in the unidirectional

I/O mode as a separate output pin for reading back data.

CS (chip select bar) is an active low control that gates the read

and write cycles. When CS is high, SDO and SDIO are in a high

impedance state. This pin is internally pulled up by a 30 kΩ

resistor to DVDD33.

AD9789

SERIAL

CONTROL

PORT

SCLK

SDO

SDIO

Figure 62. Serial Control Port

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or read operation to the AD9789 is initiated by pulling

CS low. CS stall high is supported in modes where three or

fewer bytes of data (plus the instruction data) are transferred

(see

). In these modes,

Table 7

CS can temporarily return high

on any byte boundary, allowing time for the system controller

to process the next byte. CS can go high on byte boundaries

only and can go high during either part (instruction or data)

of the transfer.

During CS stall high mode, the serial control port state machine

enters a wait state until all data is sent. If the system controller

decides to abort the transfer before all of the data is sent, the

state machine must be reset by either completing the remaining

transfers or by returning CS low for at least one complete SCLK

cycle (but less than eight SCLK cycles). Raising CS on a nonbyte

boundary terminates the serial transfer and flushes the buffer.

In streaming mode (see Table 7), any number of data bytes can

be transferred in a continuous stream. The register address is

automatically incremented or decremented (see the MSB/LSB

First Transfers section). CS must be raised at the end of the last

byte to be transferred, thereby ending streaming mode.

Communication Cycle—Instruction Plus Data

There are two parts to a communication cycle with the AD9789.

In the first part, a 16-bit instruction word is written to the

AD9789, coincident with the first 16 SCLK rising edges. The

instruction word provides the AD9789 serial control port with

information regarding the data transfer, which is the second

part of the communication cycle. The instruction word defines

whether the upcoming data transfer is a read or a write, the

number of bytes in the data transfer, and the starting register

address for the first byte of the data transfer.

Write

If the instruction word is for a write operation, the second part

of the communication cycle is the transfer of data into the serial

control port buffer of the AD9789. Data bits are registered on

the rising edge of SCLK.

The length of the transfer (one, two, or three bytes or streaming

mode) is indicated by two bits (N1 and N0) in the instruction byte.

When the transfer is one, two, or three bytes (but not streaming

mode), CS can be raised after each sequence of eight bits to stall

the bus, except after the last byte, where it ends the cycle. When

the bus is stalled, the serial transfer resumes when CS is lowered.

Raising CS on a nonbyte boundary resets the serial control port.

During a write, streaming mode does not skip reserved or blank

registers; therefore, the user must know what bit pattern to write

to the reserved registers to preserve proper operation of the

part. It does not matter what data is written to blank registers.

Most writes to the control registers immediately reconfigure the

device. However, Register 0x16 through Register 0x1D do not

directly control device operation. They provide data to internal

logic that must perform additional operations on the data before

it is downloaded and the device configuration is changed. For

any updates to Register 0x16 through Register 0x1D to take

effect, the FREQNEW bit (Register 0x1E[7]) must be set to 1

(this bit is self-clearing). Any number of bytes of data can be

changed before updating registers. Setting the FREQNEW bit

simultaneously updates Register 0x16 through Register 0x1D.

In a similar fashion, any changes to Register 0x22 and Register

0x23 require PARMNEW (Register 0x24[7]) to be toggled from

a low state to a high state before the new values take effect.

Unlike the FREQNEW bit, PARMNEW is not self-clearing.

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