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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9789BBCZ датащи(PDF) 64 Page - Analog Devices |
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AD9789BBCZ датащи(HTML) 64 Page - Analog Devices |
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64 / 76 page  AD9789 Rev. A | Page 64 of 76 4. Configure pin mode by setting the registers in Table 85 to the values shown in the table. Table 85. Register Settings to Configure Pin Modes Register Setting 0x42 0x00 0x43 0x08 0x44 0x00 0x45 0x08 0x46 0x00 0x47 0x10 0x49 0x1C 0x4B 0x1C 0x4C 0x00 0x4D 0x00 5. Cycle the PARMNEW bit to ensure that the interface configuration was updated by first setting Register 0x24 to 0x00, and then setting Register 0x24 to 0x80. 6. Apply static LVDS data to the input ports. 7. Enable the BIST pin test by setting the registers in Table 86 to the values shown in the table. Table 86. Register Settings for BIST Pin Test Register Setting 0x48 0x80 0x4A 0x80 0x40 0x55 8. Read back the signature registers (Register 0x50 to Register 0x55) to determine the pin states (see Table 87). Table 87. Signature Register Settings Register Associated LVDS Pairs 0x50 Data bits D[7:0] 0x51 Data bits D[15:8] 0x52 Parity PAR 0x53 Data bits D[7:0] (repeated) 0x54 Data bits D[15:8] (repeated) 0x55 Parity PAR (repeated) Testing Connectivity for CMOS Interface Mode To test the connectivity of the digital data input pins in CMOS interface mode, follow these steps. 1. Ensure that the clock is enabled and that the clock common-mode level is set to its optimal value by setting the registers in Table 88 to the values shown in the table. Table 88. Register Settings to Configure the Clock Register Data Description 0x30 0x80 Enable duty cycle correction. 0x31 0xF0 Set the common-mode level of CLKN: CLKN_CML = 0xF. 0x32 0x9E Set the common-mode level of CLKP: CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0. Enable clock receiver (CLK_DIS = 1). 2. Cycle the PARMNEW bit to ensure that the digital clocks are active by first setting Register 0x24 to 0x00, and then setting Register 0x24 to 0x80. 3. Configure the CMOS interface for high speed, 32-bit bus width, 16-bit data width operation by setting the registers in Table 89 to the values shown in the table. Table 89. Register Settings for CMOS Interface Register Setting 0x20 0x08 0x21 0x61 0x22 0x1F 0x23 0x87 4. Configure pin mode by setting the registers in Table 90 to the values shown in the table. Table 90. Register Settings to Configure Pin Modes Register Setting 0x42 0x00 0x43 0x08 0x44 0x00 0x45 0x08 0x46 0x00 0x47 0x10 0x49 0x1C 0x4B 0x1C 0x4C 0x00 0x4D 0x00 5. Cycle the PARMNEW bit to ensure that the interface configuration was updated by first setting Register 0x24 to 0x00, and then setting Register 0x24 to 0x80. 6. Apply static CMOS data to the input ports. 7. Enable the BIST pin test by setting the registers in Table 91 to the values shown in the table. Table 91. Register Settings for BIST Pin Test Register Setting 0x48 0x80 0x4A 0x80 0x40 0x55 8. Read back the signature registers (Register 0x50 to Register 0x55) to determine the pin states (see Table 92). Table 92. Signature Register Settings Register Associated CMOS Pairs 0x50 Data bits D[23:16] 0x51 Data bits D[31:24] 0x52 Parity P1 0x53 Data bits D[7:0] 0x54 Data bits [D15:8] 0x55 Parity P0 |
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