AD9789BBCZ datasheet(63/76 Pages) AD

63 / 76 page

AD9789

Rev. A | Page 63 of 76

CUSTOMER BIST MODES

USING THE INTERNAL PRN GENERATOR TO TEST

QAM OUTPUT AC PERFORMANCE

The AD9789 can be configured to enable an on-chip pseudo-

random number (PRN) generator. The PRN output is connected

to the front end of the datapath and disconnects the datapath

from the input pins. In this way, the PRN generator can be used

in conjunction with the on-chip QAM encoder to generate a

QAM output. The PRN generator allows the user to measure

the ac performance of a QAM signal at the DAC output without

an external data source. To enable the internal PRN generator

via the serial port, follow these steps.

Ensure that the clock is enabled and that the clock

common-mode level is set to its optimal value by setting

the registers in Table 80 to the values shown in the table.

Table 80. Register Settings to Configure the Clock

Data

Description

0x30

0x80

Enable duty cycle correction.

0x31

0xF0

Set the common-mode level of CLKN:

CLKN_CML = 0xF.

0x32

0x9E

Set the common-mode level of CLKP:

CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.

Enable clock receiver (CLK_DIS = 1).

Configure BIST mode for PRN generation and disconnect

the inputs by setting the registers in Table 81 to the values

shown in the table.

Table 81. Register Settings to Configure PRN Generation

Setting

0x42

0x10

0x43

0x00

0x44

0x10

0x45

0x00

0x46

0x00

0x47

0x10

0x49

0x16

0x4B

0x17

0x4C

0x4E

0x4D

0x1F

0x05

0x0F

Cycle the PARMNEW bit to ensure that the digital clocks

are active by first setting Register 0x24 to 0x00, and then

setting Register 0x24 to 0x80.

Start PRN generation by setting the registers in Table 82 to

the values shown in the table.

Table 82. Register Settings to Start PRN Generation

Setting

0x48

0xAB

0x4A

0xAB

0x40

0x56

After the PRN generator is started, users can freely configure

the datapath for their desired test configuration as long as

To disable the PRN generator, write 0x00 to Register 0x40.

USING THE INTERNAL BUILT-IN SELF-TEST (BIST)

TO TEST FOR DIGITAL DATA INPUT CONNECTIVITY

The AD9789 includes an internal built-in self-test (BIST) engine

that processes incoming data and creates a signature that can be

read back via the serial port. This BIST feature can be configured

to observe the static state of the digital data input pins (L4 to

L12, M4 to M12, N5 to N12, and P5 to P12) and to reflect the

state of these pins via the signature registers (Register 0x50 to

connectivity.

Testing Connectivity for LVDS Interface Mode

To test the connectivity of the digital data input pins in LVDS

interface mode, follow these steps.

Ensure that the clock is enabled and that the clock

common-mode level is set to its optimal value by setting

the registers in Table 83 to the values shown in the table.

Table 83. Register Settings to Configure the Clock

Data

Description

0x30

0x80

Enable duty cycle correction.

0x31

0xF0

Set the common-mode level of CLKN:

CLKN_CML = 0xF.

0x32

0x9E

Set the common-mode level of CLKP:

CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.

Enable clock receiver (CLK_DIS = 1).

Cycle the PARMNEW bit to ensure that the digital clocks

are active by first setting Register 0x24 to 0x00, and then

setting Register 0x24 to 0x80.

Configure the LVDS interface for high speed, 16-bit bus

width, 16-bit data width operation by setting the registers

in Table 84 to the values shown in the table.

Table 84. Register Settings for LVDS Interface

Setting

0x20

0x08

0x21

0x41

0x22

0x1F

0x23

0x87

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