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AD9789BBCZ датащи(PDF) 52 Page - Analog Devices

номер детали AD9789BBCZ
подробное описание детали  14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
PDF  76 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9789BBCZ датащи(HTML) 52 Page - Analog Devices

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AD9789
Rev. A | Page 52 of 76
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Latency Effects on Channelizer Mode
When selecting an interface configuration in channelizer mode,
the number of DCO cycles between FS pulses (cyclesAVAIL) must
be greater than the number of DCO cycles required by the inter-
face configuration (cyclesINTERFACE). Latency consumes some of
these available DCO cycles between FS. This decrease in available
DCO cycles is a result of the round-trip propagation delay from
the FS output of the AD9789 to the respective data sample at the
input of the AD9789 (LTNCY[2:0]) in addition to the internal
latency of the device.
For a successful interface design, the following condition must
be met:
cyclesAVAIL ≥ cyclesINTERFACE + LTNCY[2:0] + 2
CMOS Interface Timing
When the AD9789 is configured with a CMOS interface
(CMOS_CTRL = CMOS_BUS = 3.3 V), a CMOS data clock
output signal, DCO, is provided to drive data from the data
source. The output signal operates at the input data rate, which
is equal to fDAC/16 when DCODIV = 1. CMOS data on the bus is
sampled on the rising edge of an internal sampling clock (DSC).
Note that the frequency of DCO is equal to the frequency of
DSC and the phase relationship between DCO and DSC is
determined by DSCPHZ (Register 0x23[7:4]).
The timing of the input data is referenced to DCO for a given
phase of DSC. The CMOS data input timing over temperature is
shown in Table 68 for DCO_INV = 0 (Register 0x20[4]),
DSCPHZ = 0 (Register 0x23[7:4]), and DCODIV = 1 (Register
0x22[6:4]). Table 68 also shows the data valid window (DVW).
The data valid window is the sum of the setup and hold times of
the interface. DVW is the minimum amount of time that valid
data must be presented to the device to ensure proper sampling.
Table 68. CMOS Data Input Timing with Respect to DCO
Temperature
Min tS (ns)
Min tH (ns)
Min DVW (ns)
−40°C
4.9
−1.4
3.5
+25°C
5.1
−1.6
3.5
+85°C
5.3
−1.7
3.6
−40°C to +85°C
5.3
−1.4
3.9
For any value of DSCPHZ greater than 0, the setup and hold
times shift by increments of tDCO/16, where tDCO is the period of
the data clock.
tS = 5.3 ns − ((tDCO/16) × DSCPHZ)
tH = 0.24 ns + ((tDCO/16) × DSCPHZ)
DCO
INPUT
DATA
DSC
tS
tH
Figure 100. CMOS Input Timing
In some interface modes, the delay from the rising edge of DCO
to the rising edge of FS needs to be known. This delay is summa-
rized over temperature in Table 69.
DCO
FS
DSC
tD
Figure 101. CMOS_DCO to CMOS_FS Delay
Table 69. Timing Delay Between CMOS_DCO and CMOS_FS
Temperature
tD, MAX DCO to FS (ns)
tD, MIN DCO to FS (ns)
−40°C
0.64
0.28
+25°C
0.71
0.4
+85°C
0.85
0.49
−40°C to +85°C
0.85
0.28



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