AD9789BBCZ datasheet(33/76 Pages) AD

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AD9789

Rev. A | Page 33 of 76

The two interpolating BPF center frequency registers together compose the 16-bit center frequency of the 16× band-pass interpolation

filter. For more information about programming these registers, see the Digital 16× Tunable Band-Pass Filter section.

Table 28. Interpolating BPF Center Frequency Registers (Address 0x1C and Address 0x1D)

Address

Bit Name

Description

0x1C

FC[7:0]

Center frequency, Bits[7:0]

0x1D

FC[15:8]

Center frequency, Bits[15:8]

Table 29. Frequency Update Register (Address 0x1E)

Bit

Name

Description

FREQNEW

Setting this bit to 1 updates the derived registers in the AD9789. This bit must be set for changes to Register 0x16

through Register 0x1D to take effect. This self-clearing bit is reset to 0 after the derived registers are updated.

[6:0]

Reserved

Reserved.

Table 30. Hardware Version Register (Address 0x1F)

Bit

Name

Description

[7:4]

Reserved

Reserved.

[3:0]

VER[3:0]

This read-only register indicates the version of the chip (0011).

Table 31. Interface Configuration Register (Address 0x20)

Bit

Bit Name

Description

CMOS_BUS

This bit reflects the state of the CMOS_BUS pin (L14).

CMOS_CTRL

This bit reflects the state of the CMOS_CTRL pin (M14).

Reserved

Reserved.

DCO_INV

When set to 1, the DCO pin is inverted.

IF_MODE

This bit sets the data interface mode.

0 = channelizer mode. Supports all available interface widths and 8- and 16-bit word widths. Supports maximum

fBAUD of fDAC/48.

1 = quadrature digital upconverter (QDUC) mode. Supports 32-bit interface, 16-bit word mode only. Supports

maximum fBAUD of fDAC/16.

CHANPRI

This bit selects the channel prioritization value (used in channelizer mode only).

0 = device expects input samples only for those channels that are enabled.

1 = device expects data for all four channels. Data for disabled channels is expected and must be sent, but this

data is discarded by the AD9789.

[1:0]

PAR[1:0]

These bits set the parity checking. For more information, see the Parity section.

Setting

Parity Checking

Parity checking deactivated

IQ parity (a value of 0 is expected on the I channel and a value of 1 is expected on the

Q channel)

Even parity

Odd parity

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