AD9789BBCZ datasheet(36/76 Pages) AD

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AD9789

Rev. A | Page 36 of 76

Table 38. Mu Delay Control 1 Register (Address 0x2F)

Bit

Bit Name

Description

SEARCH_TOL

This bit specifies the accuracy of the phase search. The optimal value for this bit is 1.

0 = not exact: the search can find a phase within two values of the desired phase.

1 = exact: the search finds the exact phase specified.

SEARCH_ERR

This bit configures the search behavior when an error is encountered.

0 = stop on error.

1 = retry on error.

TRACK_ERR

This bit configures the track behavior if the controller does not find the desired phase. The optimal value for

this bit is 0.

0 = continue on error.

1 = reset on error.

[4:0]

GUARDBAND[4:0]

These bits set the guard band value. The guard band is defined as follows:

GUARDBAND[4:0] × 8 = number of mu delay codes of guard band from the endpoints

If the search mode is alternating, the search proceeds in both directions until the guard band is reached in one

direction. When the guard band is reached, the search continues only in the opposite direction. If the desired

phase is not found before the guard band is reached in the second direction, the search reverts to the alternating

mode and continues looking within the guard band. The search fails if the mu delay reaches the endpoints.

For more information, see the Mu Delay Controller section.

Setting

Guard Band

00000

…

01011

11 (default)

…

11111

Table 39. Mu Control Duty Cycle Register (Address 0x30)

Bit

Bit Name

Description

Duty cycle

correct enable

Setting this bit to 1 turns on the mu control duty cycle correction circuitry. Turn on this function before

enabling the mu controller. Along with the phase comparator boost (enabled in Register 0x3E[5]), this

function allows for more robust operation of the mu controller over the entire operating speed of the part.

INC_DEC

Reserved (factory use only).

[5:0]

MANUAL_ADJ[5:0]

Reserved (factory use only).

Table 40. Clock Receiver 1 Register (Address 0x31)

Bit

Bit Name

Description

[7:4]

CLKN_CML[3:0]

These bits adjust the common-mode level at the CLKN pin. The recommended value for these bits and the

CLKP_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section.

[3:0]

Reserved

Reserved.

Table 41. Clock Receiver 2 Register (Address 0x32)

Bit

Bit Name

Description

CLK_DIS

This bit disables or enables the clock receiver. When the AD9789 powers up, this bit is set to 0 to prevent

severe output noise that occurs on power-up with no clock. When the DAC clock is stable, set this bit to 1.

0 = disabled.

1 = enabled.

Reserved

Reserved (factory use only; leave at default value).

PSIGN

This bit specifies the sign for the CLKP_CML bits.

0 = negative (recommended).

1 = positive.

[4:1]

CLKP_CML[3:0]

These bits adjust the common-mode level at the CLKP pin. The recommended value for these bits and the

CLKN_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section.

NSIGN

This bit specifies the sign for the CLKN_CML bits.

0 = negative (recommended).

1 = positive.

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