MPC8315ECVRAGDA datasheet(107/112 Pages) FREESCALE

107 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

107

System Design Information

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 63, one to each of the AVDD pins. By providing

independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is

reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias. Note that the RC filter results in

lower voltage level on AVDD. This does not imply that the DC specification can be relaxed.

Figure 63 shows the PLL power supply filter circuit.

Figure 63. PLL Power Supply Filter Circuit

26.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8315E system, and the

MPC8315E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that

the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pins

of the device. These decoupling capacitors should receive their power from separate VDD, NVDD,

GVDD, LVDD, and GND power planes in the PCB, utilizing thick and short traces to minimize

inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others

may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, NVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip

capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the

quick response time necessary. They should also be connected to the power and ground planes through two

vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

VDD

AVDD (or L2AVDD)

2.2 µF

GND

Low ESL Surface Mount Capacitors

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